Heretofore, it is known that a processor or a cache memory (such as an SRAM memory of a processor) can operate at a much faster rate than main memory (typically made of DRAM). Thus, in the prior art, it is known to use a memory buffer or write buffer interfacing between the processor or the cache memory of the processor (hereinafter collectively referred to as "processor" for either the processor or the cache memory of the processor) and the main memory. The write buffer stores digital signals, representative of digital data, from the processor to be written into the main memory. Once the data from the processor is stored in the write buffer, the processor then can continue with other operations while the write buffer operates independently to write the data from the write buffer into the main memory.
One of the problems encountered in the prior art is if a read operation to the main memory is initiated by the processor, while the contents of the write buffer are not empty. This could cause a problem if the read operation attempts to read from an address from the main memory where a previous write operation data is still in the write buffer. The read operation would then retrieve from the main memory data that has not yet been updated by the data from the write buffer. One prior art solution is to "flush" the write buffer prior to each read operation from the processor to the main memory. By flushing, it is meant that the read operation of the processor to the main memory is held up while the contents of the write buffer are all written out to the main memory. This prior art solution is typified in the device part R3081 manufactured by Integrated Device Technology (IDT) of San Jose, Calif. Whenever a read address occurs and there is data in the write buffer, the entire contents of the write buffer is "flushed" before the read operation is serviced. The problem with this prior art is the overhead associated with having to "flush" the write buffer upon every occurrence of a read operation.
In the reference entitled "Computer Architecture A Quantitative Approach" by John Hennessy, it appears that a suggestion was made that upon a read operation, "the contents of the write buffer on a read miss [operation] are checked and if there are no conflicts and the memory system is available, let the read miss [operation] continue". In addition, it is believed that write buffers from IDT operate by flushing the entire write buffer if the read address matches one of the valid addresses in the write buffer.
Since the read operation dominates cache access and is ultimately related to the performance of the processor, it is therefor desireable to minimize the overhead i.e. waiting, associated with a read operation.